The present invention relates to a method of forming semi-conductor hetero interfaces with extremely flat interfaces that are particularly desirable to produce micro MOS transistors, quantum devices and the like.
In recent years, methods to smooth hetero interfaces have been emphatically studied as one of the key technologies to produce next generation devices with sub-micron structures, such as quantum devices, MOS transistors, etc.
With the help of drawings, one of the conventional methods of forming semiconductor hetero interfaces will be explained, The steps in a conventional method of forming silicon oxide interfaces are illustrated in FIG. 8. Item 80 is a silicon substrate, and its cross-sectional view is shown in FIG. 8(a). The surface condition of the silicon substrate 80 is shown immediately after stripping off the wet oxide interface by hydrogen fluoride. The wet oxide interface had been formed by wet oxidation after cleaning the substrate by the RCA method (a cleaning method using a solution of hydrogen fluoride, ammonia, hydrogen peroxide, sulfuric acid, hydrochloric acid, etc). The substrate was cleaned in order to remove the layer formed by such processes as slicing, grinding and the like, with resultant lowering of the interface level further down into the silicon substrate 80.
Since formation of the wet oxide layer has a high oxidation progress speed, it is not suitable for forming an ultra thin oxide layer. Instead, dry oxidation wherein thermal oxidation takes place in dry ambient seems more advantageous for forming an ultra thin gate oxide layer. However, it has been pointed out that dry oxidation has a drawback of deteriorated dielectric breakdown voltage presumably due to the roughness of the oxidation interface. M. Niwa et al. J. Electrochem. Soc. 139(1992)901. Therefore, the case where the wet oxide layer was removed will be explained in FIG. 8.
The silicon substrate 80 with the wet oxide layer stripped off as explained in the foregoing is then thermally treated in dry oxygen ambient at 900.degree. C. by means of an electric furnace. As a result, a dry oxide layer 81 of approximately 10 nm in thickness is formed as shown in FIG. 8(b).
To eliminate oxide layer defects such as pinholes, etc., the substrate is subsequently annealed in dry nitrogen gas for 20 minutes at 950.degree. C. The mechanism involved with formation of the silicon oxide interface 82 is not yet known, but it is considered closely related to the size effect of the oxidizing species and the presence of silanol groups within the oxide layer. In other words, since O.sub.2 molecules are larger than H.sub.2 O molecules, and there cannot be any silanol groups serving as a structural buffer in dry oxidation, the oxidizing species do no enter into the silicon lattice positions uniformly, but infiltrate through the (111) facet having the longest net bond length, to react with silicon atoms. Therefore, in the case of dry oxidation, specific channels through which the oxidizing species infiltrate are formed, and oxidation is considered to develop through such channels. The Debye length for the case of dry oxide layer is about 15 nm.
In the present invention, a predominant portion of oxide layer formation takes place in the initial process region of oxidation where its mechanism is not yet known. Only towards the end of the layer formation process, namely, at the stage of forming the oxide layer in the vicinity of silicon oxide interface, does there seem to exist the possibility of oxidation taking place according to the reaction law of Deal-Grove. Therefore, the relatively large roughness height as observed in FIG. 8(b) is presumably attributed to the initial reaction between the silicon atoms and the oxidizing species that first entered the lattice through channels relatively easy to infiltrate like the (111) facet.
In addition, there are various kinds of surface irregularities appearing sectionally on the exterior of the roughness shown in FIG. 8(a). Each respective surface has its own speed of oxidation, resulting in the more complicated roughness contour of the oxide interface 82, as illustrated in FIG. 8(b).
After this gate oxide layer is formed, a gate electrode 83 consisting of polysilicon and serving as an electrode is deposited. FIG. 8(c) shows a cross-sectional view of the substrate after the gate electrode 83 was formed. An observation of the surface by transmission electron microscopy showed the rms (root mean square) figure of the interface roughness to be about 1.5 nm.
When a transistor operation is performed using this gate electrode 83, an inversion layer 84 is formed in the boundary region between the gate oxide layer 81 and the uppermost layer of the substrate 80, namely, in the oxide interface region, where a strong electric field is being applied.
Electrons 85 contributing to the transistor operation move at a high speed through the inversion layer 84. Due to the existence of the oxide interface roughness, the moving electrons 85 are scattered with a resultant reduction in the electron mobility. However, the foregoing constitution accompanied by dimensional restrictions due to the integration density increase as experienced in recent years has brought about a problem of deteriorated device characteristics caused by a mobility reduction due to scattering of electrons in transit at interfaces, a dielectric breakdown failure in ultra thin oxide layers and the like.